In traditional circuit layout for a semiconductor die, features are arranged most densely in the substrate and at the same or lower density in subsequent wiring layers formed above the substrate. Pitch (the center-to-center distance between features of an integrated circuit) generally has been relaxed in higher layers due to the difficulty of accurately patterning and etching features over a surface which is not perfectly planar. Topography and deviations from planarity tend to increase in higher layers. Moreover, for simplicity of layout, it is usual to make shorter connections in lower wiring layers, and longer connections in higher wiring layers. As wiring is longer in higher layers, slowing device speed, it has been seen to be advantageous to increase the width and thickness of the wiring to lower its resistance, which has also tended to increase pitch at higher layers.
It has become increasingly important to increase device density, fitting more devices into a smaller substrate area. Increased pitch in higher layers has generally been acceptable, as the device density has been limited by feature density in the substrate, and not by the pitch of above-substrate wiring.
If, however, devices are formed entirely above the substrate, pitch of above-substrate layers becomes more important. Smaller pitch increases lithography costs, however, increasing overall device cost. There is a need, therefore, for above-substrate pitch to be minimized while minimizing overall cost.